1. Field of the Invention
This invention relates generally to the field of analog and/or digital circuit design and, more particularly, to phase-locked loop (PLL) design.
2. Description of the Related Art
A phase-locked loop (PLL) is an electronic circuit, in which a voltage- or current-driven oscillator is constantly being adjusted to lock on (or match in phase) the frequency of an input signal. Therefore, PLLs are useful for providing stability for communications channels by keeping them set to specific respective frequencies. In addition, PLLs are also used for generating signals, modulating or demodulating signals, reconstituting a particular signal with less noise, or multiplying/dividing a frequency. In general, PLLs are widely used in applications requiring a high degree of noise immunity and narrow bandwidth, for example wireless communications that employ signal-carrying methods of phase modulation (PM), frequency modulation (FM), or amplitude modulation (AM). Because of the high frequencies usually present in microwave applications, most all components of PLL systems used therein are typically constructed of discrete circuits. For many of the communication system applications where frequencies are usually in the 100 MHz range, phase-locked loop devices are typically manufactured as integrated circuits (ICs) due to their low cost versus high performance. PLLs are also commonly used for digital data transmission and in applications that process analog information.
Typically a PLL consists of a voltage-controlled oscillator (VCO) tuned using a special semiconductor diode called a varactor. When part of a VCO, a varactor is typically used as a variable capacitance in an LC oscillator configuration, where the junction capacitance of the varactor's PN junction can be varied by changing the reverse voltage across the PN junction. The VCO is initially tuned to a frequency, typically called the center frequency, close to the desired receiving or transmitting frequency. Typically this means that the VCO seeks and locks onto a desired frequency determined by the output of a crystal-controlled reference oscillator through a circuit called a phase detector. This is accomplished through the design of a feedback loop. If the VCO frequency departs from the selected frequency determined by the crystal reference, the phase detector produces control voltage that is applied to the varactor, thus bringing the VCO back to the reference frequency. The frequency of the VCO when no control voltage is applied to the inputs of the VCO is the center frequency. In general, the PLL, VCO, reference oscillator, and phase comparator together comprise a frequency synthesizer. Typically, wireless equipment that utilizes the type of frequency control described above is said to be frequency-synthesized.
FIG. 1 illustrates the block diagram of a typical PLL. The PLL configuration shown includes a phase detector (PD) 102 coupled to a loop filter 106 through an amplifier 104, with the output of loop filter 106 coupled to a VCO 108. The output of VCO 108 is fed back to PD 102 completing the loop. A reference input signal vi(t) 120 is provided to PD 102. The output vc(t) 122 of loop filter 106 provides the control voltage input for VCO 108, generating the PLL output signal vo(t) 124. As previously stated, by providing vc(t) 122 to VCO 108, the frequency of vo(t) 124 is brought back to the selected frequency determined by reference input vi(t) 120. For further flexibility, many PLLs also include a loop frequency divider (not shown) coupled to the output of VCO 108, with the output of the loop frequency divider feeding into PD 102.
One problem associated with PLLs and PLL design is the introduction of PLL phase noise due to the VCO. For IC PLLs, process variation, temperature, and biasing typically lead to a need for PLL loop component tolerance compensation. Consequently, improvements sought in PLL design have included PLL compensation loop filter size reduction (smaller component values), improved lock time, and virtual elimination of non-linear locking behavior of the PLL. These issues have been addressed in a variety of ways when designing IC PLLs. In some PLLs, compensation has been implemented based on monitoring the control voltage. If the control voltage reaches some upper or lower limit, a new set of varactors is switched in or out of the VCO in order to bring the control voltage level down or up, respectively. Generally, the non linear nature of the phase frequency detector in the PLL and the limited bandwidth of the PLL itself may result in unwanted side effects when utilizing control voltage based solutions. For example, the speed at which the control voltage rises is proportional to the PLL bandwidth. Thus, while opening the loop bandwidth may present a solution, the reference frequency filtration will suffer. At the same time, the presence of phase slips in the lock acquisition phase can further slow down the decision point.
Another approach involved in PLL compensation is based on monitoring the phase slips that occur when a phase detector goes beyond its linear range. Typically, phase detectors have a limited frequency range difference within which they can allow the PLL to lock on to the desired frequency. If there is an excessive difference between the two input terminals of the phase detector, a phase slip may occur in which the detector generally pumps in the wrong direction. By monitoring the occurrence of these phase slip events, a trimming strategy can typically be devised. However, by definition, the reference and feedback inputs of the phase detector must accumulate enough phase error to trigger this event. Therefore, as the frequency error between the two input terminals is reduced, the rate of the phase slips is reduced as well, thus providing an inconsistent locking time. For example, if the upper limits of the VCO differ from the lock frequency by 1 Hz, then it will take one second for a 2π phase slip to occur before a new VCO range can be switched in.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.